Data transmission method and data transmission system

ABSTRACT

USB transmission and reception devices are provided. A USB transmission device comprises a first interface to receive display port (DP) data via N lanes at a first link rate, wherein N is an integer greater than 1; and a switching re-timer including a plurality of de-serializer circuits to de-serialize the received DP data, a plurality of decoder circuits to decode the de-serialized DP data, a plurality of multiplexer circuits to multiplex the decoded de-serialized DP data received via each of the N lanes into 1/M lanes, wherein M is an integer greater than 1, a plurality of encoder circuits to encode the multiplexed DP data, and a plurality of serializer circuits to serialize the encoded multiplexed DP data and output the serialized multiplexed DP data on each of the N/M lanes at a second link rate, the second link rate being equal to the first link rate multiplied by M.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.16/119,988, filed Aug. 31, 2018, and entitled “Data Transmission Systemand Data Transmission Method”, which claims the benefit of priority toU.S. Provisional Patent Application No. 62/570,879, filed Oct. 11, 2017,and entitled “DP Link Rate Doubling/Halving Bit-Level Re-Timers”. Theaforementioned applications are incorporated herein by reference intheir entirety.

TECHNICAL FIELD

The present disclosure relates to a data transmission method that hasDisplayPort (DP) and Universal Serial Bus Universal Serial Bus (USB) onUSB Type-C connector.

BACKGROUND

DP Alt Mode on USB Type-C enables concurrent transport of USB traffic(both USB3.x SS and USB2) and DP traffic over a standard USB Type-Cconnector. The USB Type-C connector supports 4 pairs of high-speeddifferential signaling with a bit rate up to 10 Gbps/pair and 2 pairs ofpins for a USB2 differential signal (up to 480 Mbps), as depicted inFIG. 7. Only one of the 2 pairs, named A6/A7 and B6/B7 in FIG. 7, ofUSB2 pins is used for USB2 transport. The pair that is selected dependson the USB Type-C plug connector orientation.

DP Alt Mode on USB Type-C specification enables either (1) 2 lanes of DPMain Link concurrent with USB3.x SS and USB2 or (2) 4 lanes of DP MainLink concurrent with USB2 without USB3.x SS.

SUMMARY Problems to be Solved

For applications such as AR (augmented reality) and VR (virtualreality), there is a growing desire to have the maximum-bandwidth DPtransport of 4-lane Main Link at the highest DP link rate of 8.1Gbps/lane (called HBR3 link rate) concurrent with USB3.1 SS transport.There is one approach that enables this concurrency by routing USB3.1 SStraffic to 2 pairs of USB2 pins on a USB Type-C connector while routingall 4 lanes of DP Main Link to the 4 pairs of high-speed differentialsignal pins. This approach, however, has the drawbacks as below:

(1) Requires more complex signal multiplexing/routing

(2) Requires tunneling of USB2 traffic through USB3.1 SS traffic

(3) Requires a captive cable with USB Type-C plug connector only on oneend

BRIEF SUMMARY

The present disclosure describes technology enabling the concurrenttransport of USB traffic and DP 4 Lane equivalent traffic over USBType-C connector without drawbacks such as requirements of more complexsignal multiplexing/routing.

According to one aspect of the present disclosure, a data transmissionsystem includes a transmitter having a first switching re-timer and areceiver having a second switching re-timer. The first switchingre-timer is configured to double a link rate per lane and halve thenumber of lanes, and the second switching re-timer is configured tohalve the doubled link rate and double the halved number of lanes.

According to another aspect of the disclosure, a data transmissionsystem includes a transmitter having a first switching re-timer and areceiver having a second switching re-timer. The first switchingre-timer is configured to multiply a link rate per lane by M where Mdenotes an integer of 2 or more, and multiply the number of lanes by1/M, and the second switching re-timer is configured to multiply theM-multiplied link rate by 1/M and multiply the 1/M-multiplied number oflanes by M.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates DP Alt Mode on USB Type-C with Switches or SwitchingRe-timers;

FIG. 2 illustrates DP Alt Mode on USB Type-C with DP Link RateDoubling/Having-Capable Switching Re-timers;

FIG. 3 illustrates Internal Paths of DP Re-timers with Link RateDoubling/Halving Capabilities;

FIG. 4 illustrates Lane Multiplexing and De-multiplexing Alignment

FIG. 5 illustrates DP Alt Mode Discovery and Configuration through USBPD Controllers;

FIG. 6 illustrates DP 2-lane Main Link Re-timing without Link RateDoubling/Halving;

FIG. 7 illustrates the USB Type-C Connector Receptacle Interface.

DETAILED DESCRIPTION

USB Type-C devices include switches to support a plug connectororientation flip-ability feature. The switches for DP Alt Mode on USBType-C devices also have the ability to select either USB3.x SS signalsor DP signals for Main Link Lane 2 and Lane 3 as shown in FIG. 1. Inorder to avoid high-speed signal quality degradation over the switch, itis becoming common for the switch to have PHY signal re-timer capability(“switching re-timer”).

As depicted in FIG. 7, there are only four pairs of high-speeddifferential signal pins on a USB Type-C connector, DP Alt Mode on USBType-C USB Host/DP Source is only able to support either (1) DPtransport over 2 lanes of DP Main Link plus USB3.x SS transport or (2)DP transport over 4 lanes of DP Main Link without USB3.x SS transport.

With the disclosure described in this document, the Switching Re-timersare substituted with the Switching Re-timer with DP Link RateDoubling/Lane Count Halving capability (“DP Link Rate Doublingre-timer”) on the USB Host/DP Source side and Switching Re-timer with DPLink Rate Halving/Lane Count Doubling capability (“DP Link Rate Halvingre-timer”) on the USB Device/DP Sink side as shown FIG. 2. DP Main Linkdata for Lane 0 and Lane 1 are multiplexed on one differential pairwhile DP Main Link data for Lane 2 and Lane 3 are multiplexed on theother differential pair reserved for DP main link transport in Type CAlt Mode, thus leaving the other two pairs available for USB3.x SStraffic only.

DP Link Rate Doubling/Halving Operations

Internal paths of DP Link Rate Doubling re-timer and DP Link RateHalving re-timer are shown in FIG. 3.

The DP Link Rate Doubling re-timer recovers the link symbol clock(1×_LSCLK) from a RX CDR (Clock to Data Recovery) circuit. The clockdoubling circuit generates 2×_LSCLK that is used by 2-lanes-to-1-lanemultiplexing circuit that multiplexes 9-bit link symbols from Lane 0 andLane 1 (or Lane 2 and Lane 3). The 2×_LSCLK is also used both byANSI8b/10b encoders and by TX PLL that generates 2× serial bit clock forthe serializer circuit.

The DP Link Rate Halving re-timer recovers the 2× link symbol clock(2×_LSCLK) from RX CDR circuit. This recovered clock (2×_LSCLK clock) isused to decode the doubled ANSI8b/10b incoming stream and initiate the1-lane-to-2-lanes de-multiplexing function. Following this, the 1×_LSCLKgenerated by the clock divider circuit, is used by 1-lane-to-2-lanesde-multiplexing circuit to de-multiplexe the 9-bit link symbols to Lane0 and Lane 1 (or Lane 2 and Lane 3). This 1×_LSCLK is also used both byANSI8b/10b encoders and by the TX PLL that generates 1× serial bit clockfor the serializer circuit to regenerate a standard DP bit stream.

The DP Standard protocol mandates the periodic transmission ofANSI8b/10b K28.5 character (known as comma character) in the same linksymbol clock cycles across all the lanes.

Both the multiplexing circuit and the de-multiplexing circuit in theabove re-timers use link symbol corresponding to ANSI8b/10b K28.5(“K28.5 link symbol”) as a marker for multiplexing from/de-multiplexingto proper lanes as described below and shown in FIG. 4.

-   -   When the multiplexing circuit in the DP Link Rate Doubling        re-timer receives the K28.5 link symbol from both Lane 0 and        Lane 1 ANSI8b/10b Decoders in the same 1×_LSCLK cycle, it pushes        K28.5 link symbol to ANSI8b/10b Encoder #0 ahead of K28.5 link        symbol from Lane 1    -   When the de-multiplexing circuit in the DP Link Rate Halving        re-timer receives two consecutive K28.5 link symbols, it pushes        the first K28.5 link symbol to Lane 0 ANSI8b/10b Encoder and the        second K28.5 link symbol to Lane 1 ANSI8b/10b Encoder

DP Link Rate Doubling/Halving Re-Timers Discovery

As per the DP Alt Mode on USB Type-C specification, a switching re-timerhas a companion USB PD controller that manages the DP Alt Modecapability discovery and configuration through USB PD communication overCC line on a USB Type-C connector pin. A USB PD controller controls thecompanion switching re-timer through an embedded communication channelsuch as I2C that is not exposed to USB Type-C connector pins as shown inFIG. 5.

The DP Link Rate Doubling/Halving re-timers discover each other throughtheir companion USB PD controllers using USB PD VDM (Vendor DefinedMessage).

Link Establishment Between DP Link Rate Doubling/Halving Re-Timers

The DP Link Rate Doubling/Halving re-timers declare themselves as LTTPR(Link Training Tunable PHY Repeater) as defined in DisplayPort StandardVer. 1.4. They both declare the support of up to 4 Main Link lanes at upto HBR3 link rate (that is, up to 8.1 Gbps/lane).

When the DP Source initiates DP Link Training over 4 lanes of Main Link,DP Link Rate Doubling re-timer on the DP Source side indicates thetraining at the 2× serial bit rate over 2 lanes to the DP Link RateHalving re-timer on the DP Sink side by setting Bit 4 ofTRAINING_PATTERN_SET DPCD register (a debug mode enable bit that doesnot get set during a normal operation) in the AUX write transaction tothat DPCD register at the beginning of DP Link Training.

As the DP Link Rate Halving re-timer on the DP Sink side converts itback to 1× serial bit rate over 4 Main Link lanes, the conversion to 2×serial bit rate over 2 lanes between the DP Link Rate Doubling re-timerand the DP Link Rate halving re-timer is transparent to both DP Sourceand DP Sink.

In case the DP Source initiates DP Link Training over either 2 lanes(Lanes 0 and 1) or 1 lane (Lane 0) of the Main Link, the DP Link RateDoubling re-timer clears Bit 4 of TRAINING_PATTERN_SET DPCD register to0 via the AUX write transaction to that DPCD register at the beginningof DP Link Training. With Bit 4 cleared to 0, the DP Link Rate Doublingre-timer disables the DP link rate doubling/lane count halving operationand the DP Link Rate Halving re-timer disables DP link rate halving/lanecount doubling operation as shown in FIG. 6.

The present invention has been described in connection with the abovedescription, it is not intended to limit the scope of the invention tothe particular form set forth, but on the contrary, it is intended tocover such alternatives, modifications, and equivalents as may beincluded within the spirit and scope of the inventions as defined by theappended claims.

1. A universal serial bus (USB) transmission device, comprising: a firstinterface configured to receive display port (DP) data via N lanes at afirst link rate, wherein N is an integer greater than 1; and a switchingre-timer including a plurality of de-serializer circuits configured tode-serialize the received DP data, a plurality of decoder circuitsconfigured to decode the de-serialized DP data, a plurality ofmultiplexer circuits configured to multiplex the decoded de-serializedDP data received via each of the N lanes into 1/M lanes, wherein M is aninteger greater than 1, a plurality of encoder circuits configured toencode the multiplexed DP data, and a plurality of serializer circuitsconfigured to serialize the encoded multiplexed DP data and output theserialized multiplexed DP data on each of the N/M lanes at a second linkrate, wherein the second link rate is equal to the first link ratemultiplied by M.
 2. The USB transmission device of claim 1, wherein: theUSB transmission device is USB Type-C compliant transmission device. 3.The USB transmission device of claim 2, wherein: the USB transmissiondevice is configured to operate in DP Alt Node.
 4. The USB transmissiondevice of claim 1, wherein the switching re-timer is configured to:receive USB super speed (SS) data via Y lanes at a third link rate; andoutput the USB SS data via Z lanes at the third link rate, wherein Y isequal to Z.
 5. The USB transmission device of claim 4, wherein: the Mlanes via which the DP data is output and the Z lanes via which the USBSS data is output are output to main link lines of a USB Type-Cconnector.
 6. The USB transmission device of claim 1, wherein: the USBtransmission device is a USB Type-C connector.
 7. The USB transmissiondevice of claim 6, further comprising: four pairs of high-speeddifferential signal pins.
 8. The USB transmission device of claim 7,wherein: M equals 2, and the switching re-timer is configured to outputthe multiplexed data on each of the M lanes via 2 pairs of thehigh-speed differential signal pins.
 9. The USB transmission device ofclaim 8, wherein the switching re-timer is configured to: receive USBsuper speed (SS) data via 2 lanes at a third link rate; and output theUSB SS data via 2 lanes at the third link rate over another two pairs ofthe high-speed differential signal pins.
 10. The USB transmission deviceof claim 1, wherein: N equals 4, and M equals
 2. 11. The USBtransmission device of claim 10, wherein: the switching re-timer isconfigured to recover a link symbol clock from a clock-to-data recoverycircuit.
 12. The USB transmission device of claim 11, wherein: theswitching re-timer is configured to double a speed of the link symbolclock to output the multiplexed data on each of the M lanes at thesecond link rate.
 13. A universal serial bus (USB) reception device,comprising: a first interface configured to receive display port (DP)data via N/M lanes at a first link rate, wherein M is an integer greaterthan 1, and wherein N is an integer greater than 1; a switching re-timerincluding a plurality of de-serializer circuits configured tode-serialize the received DP data, a plurality of decoder circuitsconfigured to decode the de-serialized DP data, a plurality ofde-multiplexer circuits configured to demultiplex the decodedde-serialized DP data received via each of the N/M lanes into N lanes, aplurality of encoder circuits configured to encode the demultiplexed DPdata, and a plurality of serializer circuits configured to serialize theencoded demultiplexed DP data and output the serialized demultiplexed DPdata on each of the N lanes at a second link rate, wherein the secondlink rate is equal to the first link rate divided by M.
 14. The USBreception device of claim 13, wherein: the USB reception device is USBType-C compliant reception device.
 15. The USB reception device of claim14, wherein: the USB reception device is configured to operate in DP AltNode.
 16. The USB reception device of claim 13, wherein the switchingre-timer is configured to: receive USB super speed (SS) data via Y lanesat a third link rate; and output the USB SS data via Z lanes at thethird link rate, wherein Y is equal to Z.
 17. The USB reception deviceof claim 16, wherein: the N lanes via which the DP data is received andthe Y lanes via which the USB SS data is received correspond to mainlink lines of a USB Type-C connector.
 18. The USB reception device ofclaim 13, wherein: the USB reception device is a USB Type-C connector.19. The USB reception device of claim 18, further comprising: four pairsof high-speed differential signal pins.
 20. The USB reception device ofclaim 19, wherein: N equals 2, and the switching re-timer is configuredto receive the DP data on each of the N lanes via 2 pairs of thehigh-speed differential signal pins.
 21. The USB reception device ofclaim 20, wherein the switching re-timer is configured to: receive USBsuper speed (SS) data over another two pairs of the high-speeddifferential signal pins.
 22. The USB reception device of claim 13,wherein: N equals 2, and M equals
 4. 23. The USB reception device ofclaim 22, wherein: the switching re-timer is configured to recover alink symbol clock from a clock-to-data recovery circuit.
 24. The USBreception device of claim 23, wherein: the switching re-timer isconfigured to reduce a speed of the link symbol clock in half to outputthe demultiplexed data on each of the M lanes at the second link rate.25. A data transmission system comprising: a universal serial bus (USB)transmission device, comprising: a first interface configured to receivedisplay port (DP) data via N lanes at a first link rate, wherein N is aninteger greater than 1; a first switching re-timer including a pluralityof first de-serializer circuits configured to de-serialize the receivedDP data, a plurality of first decoder circuits configured to decode thede-serialized DP data, a plurality of multiplexer circuits configured tomultiplex the decoded de-serialized DP data received via each of the Nlanes into 1/M lanes, wherein M is an integer greater than 1, aplurality of first encoder circuits configured to encode the multiplexedDP data, and a plurality of first serializer circuits configured toserialize the encoded multiplexed DP data and output the serializedmultiplexed DP data on each of the N/M lanes at a second link rate,wherein the second link rate is equal to the first link rate multipliedby M; and a USB reception device, comprising: a second interfaceconfigured to receive the DP data output from the USB transmissiondevice on N/M lanes at the second link rate; a second switching re-timerincluding a plurality of second de-serializer circuits configured tode-serialize the received DP data, a plurality of second decodercircuits configured to decode the de-serialized DP data, a plurality ofde-multiplexer circuits configured to demultiplex the decodedde-serialized DP data received via each of the N/M lanes into N lanes, aplurality of second encoder circuits configured to encode thedemultiplexed DP data, and a plurality of second serializer circuitsconfigured to serialize the encoded demultiplexed DP data and output theserialized demultiplexed DP data on each of the N lanes at the firstlink rate.